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SIS5501 - PCI/ISA Cache Memory Controller

This page provides the datasheet information for the SIS5501, a member of the SIS5502 PCI/ISA Cache Memory Controller family.

Datasheet Summary

Description

The SiS5501(PCMC) bridges between the host bus and the PCI local bus.

The SiS5501 (PCMC) monitors each cycle initiated by the CPU, and forwards it to the PCI bus if the CPU cycle does not target the local memory.

Features

  • Supports the 51060, 56766, 73590, 815100 MHz and 75 MHz Pentium Processor Supports M1 and Other Pentium Compatible CPU Supports the Pipelined Address Mode of the Pentium or the P54C Processor Integrated Second Level ( L2 ) Cache Controller - Write Through and Write Back Cache Modes - 8 bits or 7 bits Tag with Direct Mapped Organization - Supports Standard and Burst SRAMs - Supports 64 KBytes to 2 MBytes Cache Sizes - Cache Read/Write Cycle of 3-2-2-2 or.

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Datasheet preview – SIS5501

Datasheet Details

Part number SIS5501
Manufacturer Silicon Integrated System
File Size 632.88 KB
Description PCI/ISA Cache Memory Controller
Datasheet download datasheet SIS5501 Datasheet
Additional preview pages of the SIS5501 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com Pentium/P54C PCI/ISA Chipset 1 5501/5502/5503 Overview SiS5501 SiS5502 SiS5503 PCI/ISA Cache Memory Controller (PCMC) PCI Local Data Buffer (PLDB) PCI System I/O (PSIO) A whole set of the SiS5501, 5502, and 5503 provides fully integrated support for the Pentium/P54C PCI/ISA system. The chipset is developed by using a very high level of function integration and system partitioning. With the SiS5501, SiS5502, and SiS5503 chipset, only 12 TTLs (include 3 DRAM address buffer) are required to implement a low cost, high performance, Pentium/P54C PCI/ISA system. Figure 1 shows the system block diagram.
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