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HYB39S13620TQ-7 - Special Mode Registers Two color registers Burst Read

Download the HYB39S13620TQ-7 datasheet PDF. This datasheet also covers the HYB39S13620TQ-6 variant, as both devices belong to the same special mode registers two color registers burst read family and are provided as variant models within a single manufacturer datasheet.

Description

DQ2 V SSQ DQ1 DQ0 V DD N.C.

N.C.

N.C.

Features

  • These synchronous devices achieve high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with an advanced 64MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous graphics DRAM products, both electrically and mechanically. RAS, CAS, WE, DSF and CS are pulsed signals which are examined at the positive edge of eac.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYB39S13620TQ-6_SiemensSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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HYB39S128160CTL 128-MBit Synchronous DRAM Infineon Technologies
HYB39S128160FE 128-MBit Synchronous DRAM Qimonda
HYB39S128160FEL 128-MBit Synchronous DRAM Qimonda
HYB39S128160FT 128-MBit Synchronous DRAM Qimonda

Other Datasheets by Siemens Semiconductor Group (now Infineon)

Part Number Description
HYB39S13620TQ-6 Special Mode Registers Two color registers Burst Read
HYB39S13620TQ-8 Special Mode Registers Two color registers Burst Read
HYB39S16160AT-10 16 MBit Synchronous DRAM
HYB39S16160AT-8 16 MBit Synchronous DRAM
HYB39S16160CT-10 16 MBit Synchronous DRAM

Full PDF Text Transcription

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www.DataSheet4U.com Overview HYB 39S13620TQ-6/-7/-8 • High Performance: -6 -7 125 2 8 5.5 -7 125 3 7 5.5 -8 125 3 8 6 Units MHz − ns ns • Special Mode Registers • Two color registers • Burst Read with Single Write Operation • Block Write and Write-per-Bit Capability • Byte controlled by DQM0-3 • Auto Precharge and Auto Refresh Modes • Suspend Mode and Power Down Mode • 2k refresh cycles/32 ms • tAC = 5 ns • tSETUP/tHOLD = 2 ns/1 ns • Latency 2 @ 125 MHz • Random Column Address every CLK (1-N Rule) • Single 3.3 V ± 0.3 V Power Supply • LVTTL compatible inputs and outputs fCK latency 166 3 6 5.
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