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K4N51163QC - 512Mbit gDDR2 SDRAM

General Description

The 512Mb gDDR2 SDRAM chip is organized as 8Mbit x 16 I/O x 4banks banks device.

This synchronous device achieve high speed graphic double-data-rate transfer rates of up to 800Mb/sec/pin for general applications.

Key Features

  • 1.8V + 0.1V power supply for device operation.
  • 1.8V + 0.1V power supply for I/O interface.
  • 4 Banks operation.
  • Posted CAS.
  • Programmable CAS Letency : 3,4,5.
  • Programmable Additive Latency : 0, 1, 2, 3 and 4.
  • Write Latency (WL) = Read Latency (RL) -1.
  • Burst Legth : 4 and 8 (Interleave/nibble sequential).
  • Programmable Sequential/ Interleave Burst Mode 512M gDDR2 SDRAM.
  • Bi-directional Differential Data-Strobe.

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Full PDF Text Transcription for K4N51163QC (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4N51163QC. For precise diagrams, and layout, please refer to the original PDF.

http://www.BDTIC.com/SAMSUNG K4N51163QC 512M gDDR2 SDRAM 512Mbit gDDR2 SDRAM Revision 1.8 October 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMS...

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06 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.

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