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K4S281632C-TP - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

General Description

The K4S281632C is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle.

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Full PDF Text Transcription for K4S281632C-TP (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4S281632C-TP. For precise diagrams, and layout, please refer to the original PDF.

K4S281632C-TI(P) CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 2001 * Samsung Electronics reserves the right to change products o...

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une 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) Revision History Revision 0.0 (November 18, 2000) • First generation. CMOS SDRAM Revision 0.1 (June 20, 2001) • Final Specification. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the

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