Datasheet4U Logo Datasheet4U.com

SBPH400-3 - IEEE1394 3-Port 400Mbps Physical Layer

General Description

.

.

.

.

.

Key Features

  • s 3 ports fully compliant with IEEE 1394-1995 cable environment specification s Fully implements IEEE P1394a D2.0 proposal s S100, S200 and S400 speeds s IEEE P1394a proposal PHY-LINK interface s IEEE P1394a proposal Suspend/Resume s OHCI support s Per port disable s Automatic power saving s Optional isolation support s IEEE P1394a proposal arbitration enhancements s IEEE P1394a proposal register set and remote register read s Advanced Data-Strobe clock and data recovery s Digital delay-lock loo.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SBP13005 High Voltage Fast-Switching NPN Power Transistor ETC
SBP13005-O High Voltage Fast-Switching NPN Power Transistor Winsemi
SBP13007-H1 High Voltage Fast-Switching NPN Power Transistor SemiWell Semiconductor
SBP13007-H2 High Voltage Fast-Switching NPN Power Transistor SemiWell Semiconductor
SBP13007-O High Voltage Fast-Switching NPN Power Transistor WINSEMI SEMICONDUCTOR

Other Datasheets by STMicroelectronics

Part Number Description

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
® SBPH400-3 IEEE1394 3-Port 400Mbps Physical Layer PRELIMINARY DATA s s FEATURES s 3 ports fully compliant with IEEE 1394-1995 cable environment specification s Fully implements IEEE P1394a D2.0 proposal s S100, S200 and S400 speeds s IEEE P1394a proposal PHY-LINK interface s IEEE P1394a proposal Suspend/Resume s OHCI support s Per port disable s Automatic power saving s Optional isolation support s IEEE P1394a proposal arbitration enhancements s IEEE P1394a proposal register set and remote register read s Advanced Data-Strobe clock and data recovery s Digital delay-lock loop technology - no filtering capacitors s Built-in self-test (BIST) of analog and digital port logic s JTAG Test Access Port s 3.