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RC32504A - Universal Frequency Translator

Datasheet Summary

Description

The RC32504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs.

Features

  • Jitter below 100fs RMS (10kHz to 20MHz).
  • Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC).
  • PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL) ○ Operates from a 25MHz to 80MHz crystal or XO ○ APLL frequency independent of input/crystal frequency ○ Operates as a frequency synthesizer, jitter attenuator, synchronous equipm.

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Datasheet preview – RC32504A

Datasheet Details

Part number RC32504A
Manufacturer Renesas
File Size 2.69 MB
Description Universal Frequency Translator
Datasheet download datasheet RC32504A Datasheet
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RC32504A FemtoClock®2 Sub-100fs Universal Frequency Translator Datasheet Description The RC32504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a Synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications. The device is a member of the Renesas high-performance FemtoClock2 family.
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