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RC32434 - IDT Interprise Integrated Communications Processor

Datasheet Summary

Description

for MADDR[3:0] www.DataSheet4U.com and changed 4096 cycles to 4000 for MADDR[7].

(Note: MADDR was incorrectly labeled as MDATA in previous data sheet.) March 29, 2004: Added Standby mode to Table 16, Power Consumption.

April 19, 2004: Added the I2C feature.

Features

  • 32-bit CPU Core.
  • MIPS32 instruction set.
  • Cache Sizes: 8KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches.
  • 16 dual-entry JTLB with variable page sizes.
  • 3-entry instruction TLB.
  • 3-entry data TLB.
  • Max issue rate of one 32x16 multiply per clock.
  • Max issue rate of one 32x32 multiply every other clock.
  • CPU control with start, stop, and single stepping.
  • Software break.

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Datasheet preview – RC32434

Datasheet Details

Part number RC32434
Manufacturer Integrated Device Technology
File Size 1.09 MB
Description IDT Interprise Integrated Communications Processor
Datasheet download datasheet RC32434 Datasheet
Additional preview pages of the RC32434 datasheet.

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Full PDF Text Transcription

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IDTTM InterpriseTM Integrated Communications Processor www.DataSheet4U.com RC32434 Device Overview The RC32434 is a member of the IDT™ Interprise™ family of PCI integrated communications processors. It incorporates a high performance CPU core and a number of on-chip peripherals. The integrated processor is designed to transfer information from I/O modules to main memory with minimal CPU intervention, using a highly sophisticated direct memory access (DMA) engine. All data transfers through the RC32434 are achieved by writing data from an on-chip I/O peripheral to main memory and then out to another I/O module.
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