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IDT71V35761SA - 128K x 36 3.3V Synchronous SRAM

Download the IDT71V35761SA datasheet PDF. This datasheet also covers the IDT71V35761S variant, as both devices belong to the same 128k x 36 3.3v synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT71V35761 are high-speed SRAMs organized as 128K x 36.

The IDT71V35761 SRAMs contain write, data, address and controlregisters.

InternallogicallowstheSRAMtogenerateaself-timed write based upon a decision which can be left until the end of the write cycle.

Features

  • 128K x 36 memory configurations.
  • Supports high system speed: Commercial:.
  • 200MHz 3.1ns clock access time Commercial and Industrial:.
  • 183MHz 3.3ns clock access time.
  • 166MHz 3.5ns clock access time.
  • LBO input selects interleaved or linear burst mode.
  • 3.3V core power supply Functional Block Diagram LBO ADV CLK ADSC ADSP.
  • Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx).
  • Power down control.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71V35761S-Renesas.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IDT71V35761SA 3.3V Synchronous SRAMs IDT
IDT71V35761S 3.3V Synchronous SRAMs IDT
IDT71V3576S 3.3V Synchronous SRAMs IDT
IDT71V3577S 3.3V Synchronous SRAMs IDT
IDT71V3577SA 3.3V Synchronous SRAMs IDT

Other Datasheets by Renesas

Part Number Description
IDT71V35761S 128K x 36 3.3V Synchronous SRAM
IDT71V124SA 3.3V CMOS Static RAM
IDT71V416 3.3V CMOS Static RAM
IDT71V416L 3.3V CMOS Static RAM
IDT71V416S 3.3V CMOS Static RAM

Full PDF Text Transcription

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128K x 36 3.3V Synchronous SRAMs IDT71V35761S/SA 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ 128K x 36 memory configurations ◆ Supports high system speed: Commercial: – 200MHz 3.1ns clock access time Commercial and Industrial: – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ 3.3V core power supply Functional Block Diagram LBO ADV CLK ADSC ADSP ◆ Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) ◆ Power down controlled by ZZ input ◆ 3.3V I/O ◆ Optional - Boundary Scan JTAG Interface (IEEE 1149.
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