Datasheet4U Logo Datasheet4U.com

HD74LS190P - Synchronous Up / Down Decade Counter

Download the HD74LS190P datasheet PDF. This datasheet also covers the HD74LS190 variant, as both devices belong to the same synchronous up / down decade counter family and are provided as variant models within a single manufacturer datasheet.

Features

  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS190P DILP-16 pin PRDP0016AE-B P (DP-16FV) HD74LS190FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP Notes: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity).
  • EL (2,000 pcs/reel) Rev.3.00, Jul.15.2005, page 1 of 10 HD74LS190 Pin Arrangement Data B Input 1 Outputs QB 2 QA 3 Enable G 4 Inputs Down/Up 5 Outputs.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS190-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74LS190P
Manufacturer Renesas
File Size 190.65 KB
Description Synchronous Up / Down Decade Counter
Datasheet download datasheet HD74LS190P Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74LS190 Synchronous Up/Down Decade Counters Hitachi Semiconductor
HD74LS191 Synchronous Up/Down 4-bit Binary Counters Hitachi Semiconductor
HD74LS192 Synchronous Up/Down Decade Counters Hitachi Semiconductor
HD74LS193 Synchronous Up/Down 4-bit Binary Counters Hitachi Semiconductor
HD74LS194A 4-bit Bidirectional Universal Shift Registers Hitachi Semiconductor

Other Datasheets by Renesas

Part Number Description
HD74LS190 Synchronous Up / Down Decade Counter
HD74LS191 Synchronous Up / Down 4-bit Binary Counter
HD74LS191P Synchronous Up / Down 4-bit Binary Counter
HD74LS192 Synchronous Up / Down Decade Counter
HD74LS192P Synchronous Up / Down Decade Counter

Full PDF Text Transcription

Click to expand full text
HD74LS190 Synchronous Up / Down Decade Counter (signal clock line) REJ03D0452–0200 Rev.2.00 Jul.15.2005 Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down / up input.
Published: |