Datasheet Details
| Part number | 9DB836 |
|---|---|
| Manufacturer | Renesas |
| File Size | 613.28 KB |
| Description | 8-Output 3.3V HCSL PCIe Buffer |
| Datasheet |
 9DB836 Datasheet
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General Description
The 9DB836 is a zero delay/fanout buffer for PCI Express™ clocking.
3 in zero-delay mode and PCIe Gen14 in fanout mode.
The 9DB836 is a pin-compatible upgrade to the 9DB833 and 9DB834 with a Safe Power Sequence (SPS) clock input.
RiseKey Features
- Eight 0.7V current-mode differential HCSL output pairs.
- Supports zero delay buffer (ZDB) mode and fanout mode.
- Selectable bandwidth for zero delay mode.
- 50.
- 110 MHz operation in PLL mode.
- 5.
- 166 MHz operation in Bypass mode Features.
- SPS internal receiver bias network keeps input clock parked when input is floating.
- Supports both 85Ω and 100Ω output impedance with appropriate resistor selection.
- OE# pins default to controlling outputs.