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HD74LV2GT126A - Dual Bus Buffer

Description

The HD74LV2GT126A has dual bus buffer with 3

state output in a 8 pin package.

Output is disabled when the associated output enable (OE) input is low.

Features

  • The basic gate function is lined up as Renesas uni logic series.
  • Supplied on emboss taping for high-speed automatic mounting.
  • TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range :.
  • 40 to +85°C.
  • Logic-level translate function 3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V).
  • All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO.

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Full PDF Text Transcription

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www.DataSheet4U.com HD74LV2GT126A Dual Bus Buffer with 3–state Output / CMOS Logic Level Shifter REJ03D0149–0200Z (Previous ADE-205-677A (Z)) Rev.2.00 Oct.23.2003 Description The HD74LV2GT126A has dual bus buffer with 3–state output in a 8 pin package. Output is disabled when the associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE should be connected to GND through a pull-down resistor; the minimum value of the resistor is determined by the current souring capability of the driver. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.
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