Datasheet4U Logo Datasheet4U.com

HD74LS138P - 3-Line-to-8-Line Decoders/Demultiplexers

Download the HD74LS138P datasheet PDF. This datasheet also covers the HD74LS138 variant, as both devices belong to the same 3-line-to-8-line decoders/demultiplexers family and are provided as variant models within a single manufacturer datasheet.

Features

  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS138P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74LS138FPEL SOP-16 pin (JEITA) PRSP0016DH-B FP (FP-16DAV) HD74LS138RPEL SOP-16 pin (JEDEC) PRSP0016DG-A (FP-16DNV) RP Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) - EL (2,000 pcs/reel) EL (2,500 pcs/reel) Pin Arrangement Select Inputs A1 B2 C3 G2A 4 Enable G2B 5.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS138_RenesasTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74LS138P
Manufacturer Renesas
File Size 134.81 KB
Description 3-Line-to-8-Line Decoders/Demultiplexers
Datasheet download datasheet HD74LS138P Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74LS138 3-Line-to-8-Line Decoders/Demultiplexers Hitachi Semiconductor
HD74LS13 Dual 4-input Positive NAND Schmitt Triggers Hitachi Semiconductor
HD74LS132 Quadruple 2-input Positive NAND Schmitt-triggers Hitachi Semiconductor
HD74LS132 Quadruple 2-Input Positive NAND Schmitt-triggers Renesas
HD74LS132P Quadruple 2-Input Positive NAND Schmitt-triggers Renesas

Other Datasheets by Renesas

Part Number Description
HD74LS138 3-Line-to-8-Line Decoders/Demultiplexers
HD74LS165A Parallel-Load 8-bit Shift Register
HD74LS165AP Parallel-Load 8-bit Shift Register
HD74LV1G02A 2-input NOR Gate
HD74LV1G04A Inverter

Full PDF Text Transcription

Click to expand full text
HD74LS138 www.DataSheet4U.com 3-Line-to-8-Line Decoders / Demultiplexers REJ03D0434–0300 Rev.3.00 Jul.13.2005 The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Published: |