Supports four standard SPI modes (clock phase/polarity) Operates in master and slave modes Automatic control of up to four chip select lines Configurable transaction size (1 to 32 bits) Transaction size of >32 bits is possible Double Rx and TX data buffers Configurable MSB or LSB first transaction Generation frame select/load signals
9.1
SPI Control Registers
The.
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VRS51L3074
9 SPI Interface
The SPI interface of the VRS51L3074’s provides numerous enhancements compared to other vendor offerings. The SPI interface’s key features include: • • • • • • • • Supports four standard SPI modes (clock phase/polarity) Operates in master and slave modes Automatic control of up to four chip select lines Configurable transaction size (1 to 32 bits) Transaction size of >32 bits is possible Double Rx and TX data buffers Configurable MSB or LSB first transaction Generation frame select/load signals
9.1
SPI Control Registers
The SPICTRL register controls the operating modes of the SPI interface in master mode.
VRS51L3074 Datasheet
