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HYI39S512800A - 512-Mbit Synchronous DRAM

Download the HYI39S512800A datasheet PDF. This datasheet also covers the HYI39S512160A variant, as both devices belong to the same 512-mbit synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The HY[I/B]39S512[40/80/16]0A[E/T] are four bank Synchronous DRAM’s organized as 4 banks × 32MBit ×4, 4 banks × 16MBit ×8 and 4 banks × 8Mbit ×16 respectively.

Features

  • e e t 4 U . c o m This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information. 1.1.
  • Fully Synchronous to Positive Clock Edge 0 to 70 °C Operating Temperature for HYB -40 to 85 °C Operating Temperature for HYI Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programma.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYI39S512160A_Qimonda.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HYI39S512800A
Manufacturer Qimonda
File Size 1.18 MB
Description 512-Mbit Synchronous DRAM
Datasheet download datasheet HYI39S512800A Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Qimonda

Part Number Description
HYI39S512160A 512-Mbit Synchronous DRAM
HYI39S512400A 512-Mbit Synchronous DRAM
HYI39S128160F 128-MBit Synchronous DRAM
HYI39S128800F 128-MBit Synchronous DRAM
HYI39SC128160FE 128-MBit Synchronous DRAM

Full PDF Text Transcription

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June 2007 HY[B/I]39S512400A[E/T] HY[B/I]39S512800A[E/T] HY[B/I]39S512160A[E/T] www.DataSheet4U.com 512-Mbit Synchronous DRAM SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.52 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM HY[B/I]39S512400A[E/T], HY[B/I]39S512800A[E/T], HY[B/I]39S512160A[E/T] Revision History: 2007-06, Rev. 1.52 Page All 13 www.DataSheet4U.com 13 15 19 21 Subjects (major changes since last revision) Adapted internet edition Corrected operation command "Power Down / Clock suspend ...” in truth table Corrected operation command "Power Down Exit" to X (WE#) Corrected text to "After the mode register is set a NOP command is required" , chapter 3.3 Corrected text to "One clock delay is required for mode entry and exit", chapter 3.
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