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HYI39SC128160FE - 128-MBit Synchronous DRAM

Description

output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs.

Features

  • Data Mask for Read / Write control (×8) Data Mask for Byte Control (×16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 µs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: PG.
  • TSOPII.
  • 54 400 mil width This chapter lists all main features of the product family HY[B/I]39S128[8.

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Datasheet Details

Part number HYI39SC128160FE
Manufacturer Qimonda
File Size 1.15 MB
Description 128-MBit Synchronous DRAM
Datasheet download datasheet HYI39SC128160FE Datasheet

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Full PDF Text Transcription

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March 2007 www.DataSheet4U.com HYB39S C12880 0 FE HYB39S C12816 0 FE HYI39SC128800FE HYI39SC128160FE 128-MBit Synchronous DRAM Green Product SDRAM Internet Data Sheet Rev. 1.1 Internet Data Sheet HY[B/I]39SC128[800/160]FE 128-MBit Synchronous DRAM HYB39SC128800FE, HYB39SC128160FE, HYI39SC128800FE, HYI39SC128160FE Revision History: 2007-02, Rev. 1.1 Page All 9 www.DataSheet4U.com 13 Subjects (major changes since last revision) Adapted internet edition Corrected block diagram Corrected mode register definition Previous Revision: 2006-09, Rev. 1.0 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
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