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HYB18T512161BF - 512-Mbit x16 DDR2 SDRAM

Description

latched at the cross point of differential clocks (CK rising and CK falling).

All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

Features

  • The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
  • Commands entered on each positive clock edge, data and.
  • 1.8 V ± 0.1V VDD for [.
  • 25/.
  • 28/.
  • 33].
  • 2.0 V ± 0.1V VDD for [.
  • 20/.
  • 22] data mask are referenced to both edges of DQS.
  • 1.8 V ± 0.1V VDDQ for [.
  • 25/.
  • 28/.
  • 33].
  • Data masks (DM) for write data.
  • 2.0 V ± 0.1V VDDQ for [.
  • 20/.
  • 22].
  • Posted C.

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Datasheet Details

Part number HYB18T512161BF
Manufacturer Qimonda AG
File Size 2.27 MB
Description 512-Mbit x16 DDR2 SDRAM
Datasheet download datasheet HYB18T512161BF Datasheet

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Other Datasheets by Qimonda AG

Part Number Description
HYB18T512161B2F-20 512-Mbit x16 DDR2 SDRAM
HYB18T512161B2F-25 512-Mbit x16 DDR2 SDRAM
HYB18T256161BF-20 256-Mbit x16 DDR2 SDRAM
HYB18T256161BF-25 256-Mbit x16 DDR2 SDRAM
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Full PDF Text Transcription

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December 2006 www.DataSheet4U.com HYB18T 512161 B F 512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.43 Internet Data Sheet www.DataSheet4U.com HYB18T512161BF–20/22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512161BF Revision History: 2006-11, Rev. 1.
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