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HYB18T512161B2F-20 - 512-Mbit x16 DDR2 SDRAM

Description

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.

Inputs are latched at the cross point of differential clocks (CK rising and CK falling).

Features

  • The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
  • Data masks (DM) for write data.
  • 1.8 V ± 0.1V VDD for [.
  • 20/.
  • 25].
  • 1.8 V ± 0.1V VDDQ for [.
  • 20/.
  • 25].
  • Posted CAS by programmable additive latency for better.
  • DRAM organizations with 16 data in/outputs command and data bus efficiency.
  • Double Data Rate architecture:.
  • Off-Chip-Driver impedance adjustment (OCD) and On.
  • two data.

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Datasheet Details

Part number HYB18T512161B2F-20
Manufacturer Qimonda AG
File Size 1.30 MB
Description 512-Mbit x16 DDR2 SDRAM
Datasheet download datasheet HYB18T512161B2F-20 Datasheet

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Other Datasheets by Qimonda AG

Part Number Description
HYB18T512161B2F-25 512-Mbit x16 DDR2 SDRAM
HYB18T512161BF 512-Mbit x16 DDR2 SDRAM
HYB18T256161BF-20 256-Mbit x16 DDR2 SDRAM
HYB18T256161BF-25 256-Mbit x16 DDR2 SDRAM
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Full PDF Text Transcription

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June 2007 www.DataSheet4U.com HYB18T512161B2F–20/25 512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.1 Internet Data Sheet www.DataSheet4U.com HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512161B2F–20/25 Revision History: 2007-06, Rev. 1.1 Page All Subjects (major changes since last revision) Typo Changes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 05152007-ZYAH-ACMZ 2 Internet Data Sheet www.DataSheet4U.
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