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m Preliminary PLL602-14 o c . Low Phase Noise LVDS XO (12 – 24MHz Crystals) 192MHz – 384MHz U 4 t e FEATURES PIN CONFIGURATION e h S output for the 192MHz to • Low phase noise a 384MHz range t (-134 dBc at 10kHz offset). a • LVDS output. D24MHz crystal input. • 12 . to • w Integrated crystal load capacitor: no external wload capacitor required. w• Output Enable selector.
VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VDD XIN GND_BUF CLKBAR
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3.3V operation. Available in 16 Pin TSSOP or SOIC.
DESCRIPTION
The PLL602-14 is a monolithic low jitter and low phase noise (-134dBc/Hz @ 10kHz offset) XO IC with LVDS output, for 192MHz to 384MHz output range. It provides a low phase noise reference frequency using a low cost crystal. The chip delivers an output frequency of F XIN x 16.
PLL602-14 Datasheet
