NBSG14 - SiGe Differential 1:4 Clock/Data Driver

Product Overview

ON Semiconductor

Part number	NBSG14
Manufacturer	ON Semiconductor
File Size	416.46 KB
Description	SiGe Differential 1:4 Clock/Data Driver
Datasheet	NBSG14 Datasheet
Additional preview pages of the NBSG14 datasheet.

MARKING DIAGRAMS The NBSG14 is a 1 to 4 clock/data distribution chip, optimized for ultra

low skew and jitter.

Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS.

SG 14 ALYW FCBGA.
16 BA SUFFIX CASE 489.
Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 30 ps Typical Rise and Fall Times 125 ps Typical Propagation Delay RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE =.
2.375 V to.

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NBSG16M - 2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
NBSG16VS - 2.5V/3.3V SiGe Differential Receiver/Driver
NBSG53A - 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider

Published: Apr 23, 2007 |