Download the DS8640 datasheet PDF.
This datasheet also covers the DS8640N variant, as both devices belong to the same quad nor unified bus receiver family and are provided as variant models within a single manufacturer datasheet.
General Description
The DS7640 and DS8640 are quad 2-input receivers designed for use in bus organized data transmission systems interconnected by terminated 120X impedance lines The external termination is intended to be 180X resistor from the bus to the a5V logic supply together with a 390X resistor from the bus to g
Key Features
Y Low input current with normal VCC or VCC e 0V (30 mA typ)
Y High noise immunity (1 1V typ)
Y Temperature-insensitive input thresholds track bus logic levels
Y TTL compatible output
Y Matched optimized noise immunity for ‘‘1’’ and ‘‘0’’ levels
Y High speed (19 ns typ)
Connection Diagram
Dual-In-Line Package
Typical.
Note: The manufacturer provides a single datasheet file (DS8640N_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for DS8640 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
DS8640. For precise diagrams, and layout, please refer to the original PDF.
DS7640 DS8640 Quad NOR Unified Bus Receiver February 1996 DS7640 DS8640 Quad NOR Unified Bus Receiver General Description The DS7640 and DS8640 are quad 2-input receivers...
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r General Description The DS7640 and DS8640 are quad 2-input receivers designed for use in bus organized data transmission systems interconnected by terminated 120X impedance lines The external termination is intended to be 180X resistor from the bus to the a5V logic supply together with a 390X resistor from the bus to ground The design employs a built-in input threshold providing substantial noise immunity Low input current allows up to 27 driver receiver pairs to utilize a common bus Features Y Low input current with normal VCC or VCC e 0V (30 mA typ) Y High noise immunity (1 1V typ) Y Temperature-insensitive input thres
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