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NT5CC128M16IP - Industrial and Automotive DDR3(L) 2Gb SDRAM

This page provides the datasheet information for the NT5CC128M16IP, a member of the NT5CB256M8IN Industrial and Automotive DDR3(L) 2Gb SDRAM family.

Datasheet Summary

Features

  • JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
  • Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
  • Power Saving Mode - Partial Array Self Refresh (PASR) 1 - Power Down Mode.
  • Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (.

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Datasheet Details

Part number NT5CC128M16IP
Manufacturer Nanya
File Size 3.45 MB
Description Industrial and Automotive DDR3(L) 2Gb SDRAM
Datasheet download datasheet NT5CC128M16IP Datasheet
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Full PDF Text Transcription

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NTC Proprietary Level: Property DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Commercial, Industrial and Automotive DDR3(L) 2Gb SDRAM Features  JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM  Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode - Partial Array Self Refresh (PASR) 1 - Power Down Mode  Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)  Signal Synchronization - Write Leveling via MR settings 6 - Read Leveling via MPR  Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.
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