Datasheet Details
| Part number | SSTUB32868 |
|---|---|
| Manufacturer | NXP Semiconductors |
| File Size | 301.87 KB |
| Description | 1.8 V 28-bit 1 : 2 configurable registered buffer with parity |
| Datasheet |
 SSTUB32868 Datasheet
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Description
The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules.
Features
- 28-bit data register supporting DDR2.
- Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866).
- Parity checking function across 22 input data bits.
- Parity out signal.
- Controlled multi-impedance output impedance drivers enable optimal signal integrity and speed.
- Meets or exceeds SSTUB32868 JEDEC standard speed performance.
- Supports up to.