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HEF4027B-Q100
Dual JK flip-flop
Rev. 1 — 26 June 2013
Product data sheet
1. General description
The HEF4027B-Q100 is an edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground).
HEF4027B-Q100 Datasheet
