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74LVC646A - Octal bus transceiver/register

General Description

The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers.

Key Features

  • 5 V tolerant inputs/outputs for interfacing with 5 V logic.
  • Supply voltage range from 1.2 V to 3.6 V.
  • CMOS low-power consumption.
  • Direct interface with TTL levels.
  • 8-bit octal transceiver with D-type latch.
  • Back-to-back registers for storage.
  • Separate controls for data flow in each direction.
  • Supports partial power-down.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC646A Octal bus transceiver/register; 3-state Rev. 5 — 28 March 2013 Product data sheet 1. General description The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the A or B bus is clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the A or B register, or in both. With the select source inputs (SAB and SBA), stored and real-time (transparent mode) data can be multiplexed.