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74LVC623A - Octal transceiver

General Description

The 74LVC623A is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions.

This octal bus transceiver is designed for asynchronous two-way communication between data buses.

Key Features

  • 5 V tolerant inputs and outputs for interfacing with 5 V logic.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • High-impedance when VCC = 0 V.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115B exceeds 200 V.
  • CDM JESD22-C101E exceeds 1000.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC623A Octal transceiver with dual enable; 3-state Rev. 5 — 25 November 2011 Product data sheet 1. General description The 74LVC623A is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows maximum flexibility in timing. This device allows data transmission from the An bus to the Bn bus or from the Bn bus to the An bus, depending upon the logic levels at the enable inputs (pins OEAB and OEBA). The enable inputs can be used to disable the device so that the buses are effectively isolated.