Datasheet4U Logo Datasheet4U.com

NTE6508 - Integrated Circuit CMOS / 1K Static RAM (SRAM)

Description

The NTE6508 is a 1024 x 1 fully static CMOS RAM in a 16 Lead DIP type package fabricated using self

aligned silicon gate technology.

Synchronous circuit design techniques are employed to acheive high performance and low power operation.

Features

  • D Low Power Standby: 50µW Max D Low Power Operation: 20mW/MHz Max D Fast Access Time: 300ns Max D Data Retention: 2V Min D TTL Compatible Input/Output D High Output Drive: 2 TTL Loads D On.
  • Chip Address Register Absolute Maximum Ratings: (Note 1) Supply Voltage.
  • . . . . +7V Input, Output or I/O Voltage.
  • . . . . G.

📥 Download Datasheet

Datasheet Details

Part number NTE6508
Manufacturer NTE Electronics (defunct)
File Size 37.57 KB
Description Integrated Circuit CMOS / 1K Static RAM (SRAM)
Datasheet download datasheet NTE6508 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
NTE600 Silicon Varistor Temperature Compensating Diode NTE
NTE61 Silicon Complementary Transistors NTE
NTE6154 Silicon Industrial Rectifier NTE
NTE6155 Silicon Industrial Rectifier NTE
NTE6156 Silicon Industrial Rectifier NTE

Other Datasheets by NTE Electronics (defunct)

Part Number Description
NTE6507 Integrated Circuit NMOS / 8 Bit Microprocessor (MPU) w/On-Chip Clock OSC
NTE65 Silicon NPN Transistor High Voltage / Low Noise for CATV / MATV
NTE65101 Integrated Circuit 256 x 4-Bit Static Random Access Memory (SRAM)
NTE60 Silicon Complementary Transistors High Power Audio / Disk Head Positioner for Linear Applications
NTE6005 Silicon Power Rectifier Diode / 40 Amp

Full PDF Text Transcription

Click to expand full text
NTE6508 Integrated Circuit CMOS, 1K Static RAM (SRAM) Description: The NTE6508 is a 1024 x 1 fully static CMOS RAM in a 16–Lead DIP type package fabricated using self–aligned silicon gate technology. Synchronous circuit design techniques are employed to acheive high performance and low power operation. On chip latches are provided for address allowing effecient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. Features: D Low Power Standby: 50µW Max D Low Power Operation: 20mW/MHz Max D Fast Access Time: 300ns Max D Data Retention: 2V Min D TTL Compatible Input/Output D High Output Drive: 2 TTL Loads D On–Chip Address Register Absolute Maximum Ratings: (Note 1) Supply Voltage . . . . . . . . . . . . .
Published: |