MC9S12B
Features
NOTE Not all features listed here are available in all configurations. Additional information about D and B family inter-operability is given in: EB386 “HCS12 D-Family patibility Considerations” and EB388 “Using the HCS12 D_Family as a development platform for the HCS12 B family”
- 16-bit CPU12
- Upward patible with M68HC11 instruction set
- Interrupt stacking and programmer’s model identical to M68HC11
- 20-bit ALU
- Instruction queue
- Enhanced indexed addressing
- Multiplexed bus
- Single chip or expanded
- 16 address/16 data wide or 16 address/8 data narrow modes
- External address space 1MByte for Data and Program space (112 pin package only)
- Wake-up interrupt inputs depending on the package option
- 8-bit port H
- 4-bit port J
- 8-bit port P shared with PWM
- Memory options
- 64K, 128K, 256K Byte Flash EEPROM
- 1K, 2K Byte EEPROM
- 2K, 4K and 8K Byte RAM
This document contains information on a new product. Specifications and information herein are subject to change...
