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MC54F138 - 1-OF-8 DECODER/ DEMULTIPLEXER

General Description

The decoder accepts three binary weighted inputs (AO, A1, A2) and when enabled provides eight mutually exclusive active LOW outputs (O0

O7).

Key Features

  • three Enable inputs, two active LOW (E1, E2) and one active HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four F138s and one inverter. The F138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanen.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MC54F13 SCHMITT TRIGGERS DUAL 4-INPUT NAND/HEX INVERTERS
MC54F109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MC54F11 TRIPLE 3-INPUT AND GATE
MC54F125 (MC54F125 / MC54F126) 3-STATE QUAD BUFFERS
MC54F126 (MC54F125 / MC54F126) 3-STATE QUAD BUFFERS
MC54F14 SCHMITT TRIGGERS DUAL 4-INPUT NAND/HEX INVERTERS
MC54F148 8-LINE TO 3-LINE PRIORITY ENCODER
MC54F151 8-INPUT MULTIPLEXER
MC54F153 DUAL 4-INPUT MULTIPLEXER
MC54F181 4-BIT ARITHMETIC LOGIC UNIT

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com MC54/74F138 1-OF-8 DECODER/ DEMULTIPLEXER The MC54/74F138 is a high speed 1-of-8 Decoder/Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or to a 1-of-32 decoder using four F138s and one inverter.