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V62C5181024 - 128K X 8 STATIC RAM

General Description

The V62C5181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits.

It is built with MOSEL VITELIC’s high performance CMOS process.

Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

Key Features

  • s High-speed: 35, 70 ns s Ultra low DC operating current of 5mA (max. ) TTL Standby: 5 mA (Max. ) CMOS Standby: 60 µA (Max. ) s Fully static operation s All inputs and outputs directly compatible s Three state outputs s Ultra low data retention current (VCC = 2V) s Single 5V ± 10% Power Supply s Packages.
  • 32-pin TSOP (Standard).
  • 32-pin 600 mil PDIP.
  • 32-pin 440 mil SOP (525 mil pin-to-pin).

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Datasheet Details

Part number V62C5181024
Manufacturer Mosel Vitelic Corp
File Size 59.55 KB
Description 128K X 8 STATIC RAM
Datasheet download datasheet V62C5181024 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOSEL VITELIC V62C5181024 128K X 8 STATIC RAM PRELIMINARY Features s High-speed: 35, 70 ns s Ultra low DC operating current of 5mA (max.) TTL Standby: 5 mA (Max.) CMOS Standby: 60 µA (Max.) s Fully static operation s All inputs and outputs directly compatible s Three state outputs s Ultra low data retention current (VCC = 2V) s Single 5V ± 10% Power Supply s Packages – 32-pin TSOP (Standard) – 32-pin 600 mil PDIP – 32-pin 440 mil SOP (525 mil pin-to-pin) Description The V62C5181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.