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MT9LSDT872 - SYNCHRONOUS DRAM MODULE

Download the MT9LSDT872 datasheet PDF. This datasheet also covers the MT9LSDT1672 variant, as both devices belong to the same synchronous dram module family and are provided as variant models within a single manufacturer datasheet.

General Description

The MT9LSDT872 and MT9LSDT1672 are high-speed CMOS, dynamic random-access, 64MB and 128MB memories organized in a x72 configuration.

These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of clock signals CK0).

Key Features

  • JEDEC-standard 168-pin, dual in-line memory module (DIMM).
  • PC133- and PC100-compliant.
  • Registered inputs with one-clock delay.
  • Phase-lock loop (PLL) clock driver to reduce loading.
  • Utilizes 133 MHz and 125 MHz SDRAM components.
  • ECC-optimized pinout.
  • 64MB (8 Meg x 72) and 128MB (16 Meg x 72).
  • Single +3.3V ±0.3V power supply.
  • Fully synchronous; all signals registered on positive edge of PLL clock.
  • Internal p.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MT9LSDT1672_MicronTechnology.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for MT9LSDT872 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for MT9LSDT872. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs SYNCHRONOUS DRAM MODULE FEATURES • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • PC133- an...

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JEDEC-standard 168-pin, dual in-line memory module (DIMM) • PC133- and PC100-compliant • Registered inputs with one-clock delay • Phase-lock loop (PLL) clock driver to reduce loading • Utilizes 133 MHz and 125 MHz SDRAM components • ECC-optimized pinout • 64MB (8 Meg x 72) and 128MB (16 Meg x 72) • Single +3.3V ±0.

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