Download the MT9LD472A datasheet PDF.
This datasheet also covers the MT9LD272A variant, as both devices belong to the same nonbuffered dram dimms family and are provided as variant models within a single manufacturer datasheet.
General Description
The MT9LD272A(X) and MT18LD472A(X) are randomly accessed 16MB and 32MB memories organized in a x72 configuration.
They are specially processed to operate from 3V to 3.6V for low-voltage memory systems.
Key Features
JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin, dual in-line memory module (DIMM).
16MB (2 Meg x 72) and 32MB (4 Meg x 72).
Nonbuffered.
High-performance CMOS silicon-gate process.
Single +3.3V ±0.3V power supply.
All inputs, outputs and clocks are TTL-compatible.
Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN.
Full PDF Text Transcription for MT9LD472A (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
MT9LD472A. For precise diagrams, and layout, please refer to the original PDF.
www.DataSheet4U.com OBSOLETE 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs DRAM MODULE FEATURES • JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin, dual in-line memory module (...
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ard, eight-CAS#, ECC pinout in a 168-pin, dual in-line memory module (DIMM) • 16MB (2 Meg x 72) and 32MB (4 Meg x 72) • Nonbuffered • High-performance CMOS silicon-gate process • Single +3.3V ±0.3V power supply • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN • 2,048-cycle refresh distributed across 32ms • FAST-PAGE-MODE (FPM) or Extended Data-Out (EDO) PAGE MODE access cycles • Serial presence-detect (SPD) MT9LD272A(X), MT18LD472A(X) For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.
MT9LD472A Datasheet
