MT58L128L18D
FEATURES w w w
NOT REENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM MT58L128L18D, MT58L64L32D, MT58L64L36D
3.3V VDD, 3.3V I/O, Pipelined, Double-Cycle Deselect
- Fast clock and OE# access times
- Single +3.3V +0.3V/-0.165V power supply (VDD)
- Separate +3.3V isolated output buffer supply (VDDQ)
- SNOOZE MODE for reduced-power standby
- mon data inputs and data outputs
- Individual BYTE WRITE control and GLOBAL WRITE
- Three chip enables for simple depth expansion and address pipelining
- Clock-controlled and registered addresses, data I/Os and control signals
- Internally self-timed WRITE cycle
- Burst control pin (interleaved or linear burst)
- Automatic power-down
- 100-pin TQFP package
- Low capacitive bus loading
- x18, x32, and x36 options available
OPTIONS
- Timing (Access/Cycle/MHz) 3.5ns/6ns/166 MHz 4.0ns/7.5ns/133 MHz 5ns/10ns/100 MHz
- Configurations 128K x 18 64K x 32 64K x 36
- Packages 100-pin TQFP
- Operating Temperature Range...
