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ZL30281 - Three-Output PCIe Clock Generator

Datasheet Summary

Description

” 7 3.0 “Functional Description” 9 3.1 “Pin-Controlled Automatic Configuration at Reset” 9 3.2 “Local Oscillator or Crystal” 9 3.2.1 “External Oscillator” 9 3.2.2 “External Crystal and On-Chip Driver Circuit” 9 3.3 “Output Clock Configuration” 10 3.3.1 “Output Signal Format, Voltage, and Interfa

Features

  • 25 MHz Crystal or CMOS Input.
  • Generates PCIe 1, 2, 3, 4, 5, 6 Jitter-Compliant Clocks with CML Outputs.
  • Four Default Configurations Selected by Hardware Pins at Reset: - Config0: 100 MHz on Output OC1 (CML) - Config1: 100 MHz on OC1, OC2 (CML) - Config2: 100 MHz on OC1 (CML), OC2 (HSTL) - Config3: 100 MHz on OC1, OC2 (CML) and 25 MHz LVCMOS on OC3.
  • Per-Output Controls (Using SPI or I2C Interface) - Per-Output Enable/Disable and Glitchless Start/Stop (Stop Hig.

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Datasheet Details

Part number ZL30281
Manufacturer Microchip
File Size 1.28 MB
Description Three-Output PCIe Clock Generator
Datasheet download datasheet ZL30281 Datasheet
Additional preview pages of the ZL30281 datasheet.

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Full PDF Text Transcription

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ZL30281 Three-Output PCIe Clock Generator Features • 25 MHz Crystal or CMOS Input • Generates PCIe 1, 2, 3, 4, 5, 6 Jitter-Compliant Clocks with CML Outputs • Four Default Configurations Selected by Hardware Pins at Reset: - Config0: 100 MHz on Output OC1 (CML) - Config1: 100 MHz on OC1, OC2 (CML) - Config2: 100 MHz on OC1 (CML), OC2 (HSTL) - Config3: 100 MHz on OC1, OC2 (CML) and 25 MHz LVCMOS on OC3 • Per-Output Controls (Using SPI or I2C Interface) - Per-Output Enable/Disable and Glitchless Start/Stop (Stop High or Low) - Precise Output Alignment Circuitry and PerOutput Phase Adjustment • SPI or I2C Processor Interface • Tiny 5 mm x 5 mm VQFN Package Applications • PCIe Gen1 to Gen6 Clock Generation for PCIe Storage Systems, Riser Cards, JBOF, etc.
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