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L29C525 - Dual Pipeline Register

Description

The L29C525 is a high-speed, low power CMOS pipeline register.

It is pin-for-pin compatible with the AMD Am29525.

The L29C525 can be configured as two independent 8-level pipelines or as a single 16-level pipeline.

Features

  • u u u u u u u u Dual 8-Deep Pipeline Register Configurable to Single 16-Deep Low Power CMOS Technology Replaces AMD Am29525 Load, Shift, and Hold Instructions Separate Data In and Data Out Pins Three-State Outputs Package Styles Available:.
  • 28-pin Plastic DIP.
  • 28-pin Plastic LCC, J-Lead L29C525 BLOCK.

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Datasheet Details

Part number L29C525
Manufacturer LOGIC Devices Incorporated
File Size 172.32 KB
Description Dual Pipeline Register
Datasheet download datasheet L29C525 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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L29C525 DEVICES INCORPORATED Dual Pipeline Register L29C525 DEVICES INCORPORATED Dual Pipeline Register DESCRIPTION The L29C525 is a high-speed, low power CMOS pipeline register. It is pin-for-pin compatible with the AMD Am29525. The L29C525 can be configured as two independent 8-level pipelines or as a single 16-level pipeline. The configuration implemented is determined by the instruction code (I1-0) as shown in Table 2. The I1-0 instruction code controls the internal routing of data and loading of each register. For instruction I1-0 = 00 (Push A and B), data applied at the D 7-0 inputs is latched into register A0 on the rising edge of CLK. The contents of A0 simultaneously move to register A1, A1 moves to A2, and so on. The contents of register A7 are wrapped back to register B0.
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