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L29C520 - 4 x 8-bit Multilevel Pipeline Register

Description

The L29C520 and L29C521 are pinfor-pin compatible with the IDT29FCT520/IDT29FCT521 and AMD Am29520/Am29521, implemented in low power CMOS.

The L29C520 and L29C521 contain four registers which can be configured as two independent, 2-level pipelines or as one 4-level pipeline.

Features

  • u Four 8-bit Registers u Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register u Hold, Shift, and Load Instructions u Separate Data In and Data Out Pins u High-Speed, Low Power CMOS Technology u Three-State Outputs u Replaces IDT29FCT520/IDT29FCT521 and AMD Am29520/Am29521 u Package Styles Available:.
  • 24-pin PDIP.
  • 28-pin PLCC, J-Lead TABLE 1. L29C520.

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Datasheet Details

Part number L29C520
Manufacturer LOGIC Devices Incorporated
File Size 188.60 KB
Description 4 x 8-bit Multilevel Pipeline Register
Datasheet download datasheet L29C520 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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L29C520/521 DEVICES INCORPORATED 4 x 8-bit Multilevel Pipeline Register L29C520/521 DEVICES INCORPORATED 4 x 8-bit Multilevel Pipeline Register DESCRIPTION The L29C520 and L29C521 are pinfor-pin compatible with the IDT29FCT520/IDT29FCT521 and AMD Am29520/Am29521, implemented in low power CMOS. The L29C520 and L29C521 contain four registers which can be configured as two independent, 2-level pipelines or as one 4-level pipeline. The Instruction pins, I1-0, control the loading of the registers. For either device, the registers may be configured as a four-stage delay line, with data loaded into R1 and shifted sequentially through R2, R3, and R4. Also, for the L29C520, data may be loaded from the inputs into either R1 or R3 with only R2 or R4 shifting.
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