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HIP7030A2 - J1850 8-Bit 68HC05 Microcontroller

Description

The HIP7030A2 HCMOS Microcomputer is a member of the CDP68HC05 family of low-cost single-chip microcomputers.

Features

  • Fully Supports VPW Specifications of SAE J1850 Standard for Class B Data Communications Network Interface.
  • On-Chip Memory.
  • 176 Bytes of RAM.
  • 2110 Bytes of User ROM.
  • 13 Bidirectional I/O Lines.
  • 16-Bit Timer with Capture and Compare Registers.
  • Serial Peripheral Interface (SPI) System.
  • Watchdog Timer and Slow Clock Detect.
  • 10MHz Operating Frequency (5.0MHz Internal Bus Frequency) at 5V.
  • Built-In-Test Bootstrap.

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Full PDF Text Transcription

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HIP7030A2 ADVANCE INFORMATION August 1996 J1850 8-Bit 68HC05 Microcontroller Description The HIP7030A2 HCMOS Microcomputer is a member of the CDP68HC05 family of low-cost single-chip microcomputers. The integrated hardware functions provide the system designer with a complete set of building blocks for implementing a “Class B” multiplexed communications network interface, which fully conforms to the VPW Multiplexed Wiring protocol specified in SAE Recommended Practice J1850.
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