Datasheet4U Logo Datasheet4U.com

HCTS75MS - Radiation Hardened Dual 2-Bit Bistable Transparent Latch

Description

The Intersil HCTS75MS is a Radiation Hardened dual 2-bit bistable transparent latch.

Each of the two latches are controlled by a separate enable input (E) which are active low.

E low latches the output state.

Features

  • 3 Micron Radiation Hardened SOS CMOS.
  • Total Dose 200K RAD (Si).
  • SEP Effective LET No Upsets: >100 MEV-cm2/mg.
  • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ).
  • Dose Rate Survivability: >1 x 1012 RAD (Si)/s.
  • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse.
  • Latch-Up Free Under Any Conditions.
  • Military Temperature Range: -55oC to +125oC.
  • Significant Power Reduction Compared to LSTTL ICs.
  • DC Operat.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HCTS164MS 8-Bit Serial-In/Parallel-Out Shift Register Intersil
HCTS191MS Synchronous 4-Bit Up/Down Counter Intersil
HCTS20MS Radiation Hardened Dual 4-Input NAND Gate Intersil
HCTSM80101AAL High Clearance and Creepage Distance Transformers BOURNS
HCTSM80102AAL High Clearance and Creepage Distance Transformers BOURNS

Other Datasheets by Intersil (Renesas)

Part Number Description
HCTS74MS Radiation Hardened Dual-D Flip-Flop
HCTS74T Radiation Hardened Dual-D Flip-Flop with Set and Reset
HCTS00MS Radiation Hardened Quad 2-Input NAND Gate
HCTS02MS Radiation Hardened Quad 2-Input NOR Gate
HCTS04MS Radiation Hardened Hex Inverter

Full PDF Text Transcription

Click to expand full text
HCTS75MS September 1995 Radiation Hardened Dual 2-Bit Bistable Transparent Latch Pinouts 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW Q0 1 D0 1 D1 1 E 2 VCC D0 2 D1 2 Q1 2 1 2 3 4 5 6 7 8 16 1 Q0 15 1 Q1 14 1 Q1 13 1 E 12 11 GND 2 Q0 Features • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.
Published: |