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RD38F4050L0Z - (RD38F4455LVY / RD38F4050L0Z) Wireless Memory System

General Description

at any time, without notice.

Key Features

  • Device Architecture.
  • xRAM Performance.
  • Code and data segment: 128- and 256.
  • PSRAM at 1.8 V I/O : 85 ns initial Mbit density; PSRAM: 32- and 64-Mbit access, 30 ns async page reads; 65 ns density; SRAM: 8 Mbit density. initial access, 18 ns async page.
  • Top or bottom parameter configuration.
  • SRAM at 1.8 or 3.0 V I/O: 70 ns initial access.
  • Asymmetrical blocking structure.
  • Flash Performance.
  • 16-KWord.

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Datasheet Details

Part number RD38F4050L0Z
Manufacturer Intel
File Size 1.38 MB
Description (RD38F4455LVY / RD38F4050L0Z) Wireless Memory System
Datasheet download datasheet RD38F4050L0Z Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com Intel StrataFlash£ Wireless Memory System (LV18/LV30 SCSP) 768-Mbit LVQ Family with Asynchronous Static RAM Datasheet Product Features ■ ■ ■ ■ ■ Device Architecture ■ xRAM Performance — Code and data segment: 128- and 256— PSRAM at 1.8 V I/O : 85 ns initial Mbit density; PSRAM: 32- and 64-Mbit access, 30 ns async page reads; 65 ns density; SRAM: 8 Mbit density. initial access, 18 ns async page. — Top or bottom parameter configuration. — SRAM at 1.8 or 3.0 V I/O: 70 ns initial access. — Asymmetrical blocking structure. ■ Flash Performance — 16-KWord parameter blocks (Top or — Code Segment at 1.8 V I/O: 85 ns initial Bottom); 64-K Word main blocks. access; 25 ns async page read; 14 ns — Zero-latency block locking. sync reads (tCHQV); 54 MHz CLK.