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IS61DDPB42M18B - 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM

General Description

1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Common I/O read and write ports.

Synchronous pipeline read with self-timed late write operation.

Double Data Rate (DDR) interface for read and write input ports.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDPB42M18B1 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
IS61DDPB42M18B2 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
IS61DDPB42M18A 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
IS61DDPB42M18A1 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
IS61DDPB42M18A2 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM

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IS61DDPB42M18B/B1/B2 IS61DDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75 to 0.9V VREF.