IS61DDPB22M36 Datasheet PDF - Integrated Silicon Solution DDR-IIP (Burst of 2) CIO Synchronous SRAMs Specs

IS61DDPB22M36 - DDR-IIP (Burst of 2) CIO Synchronous SRAMs

This page provides the datasheet information for the IS61DDPB22M36, a member of the IS61DDPB24M18 DDR-IIP (Burst of 2) CIO Synchronous SRAMs family.

Datasheet Summary

Description

The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Features

2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common data input/output bus.
Synchronous pipeline read with self-timed late write operation.
Double data rate (DDR-IIP) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and control registering at rising edges only.
Industrial te.

Datasheet Details

Part number	IS61DDPB22M36
Manufacturer	Integrated Silicon Solution
File Size	572.22 KB
Description	DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Datasheet	IS61DDPB22M36 Datasheet
Additional preview pages of the IS61DDPB22M36 datasheet.

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Full PDF Text Transcription

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72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs. t of 2) CIO Synchronous SRAMs (2.5 Cycle Read Latency) Advanced Information May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late write operation. • Double data rate (DDR-IIP) interface for read and write input ports. • Fixed 2-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Industrial temperature available upon request. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.

Published: Jul 25, 2016 |