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IDT71V321L - HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM

Download the IDT71V321L datasheet PDF. This datasheet also covers the IDT-71V variant, as both devices belong to the same high-speed 3.3v 2k x 8 dual-port static ram family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications.

The IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port RAM.

Features

  • High-speed access.
  • Commercial: 25/35/55ns (max. ).
  • Low-power operation.
  • IDT71V321S.
  • Active: 250mW (typ. ).
  • Standby: 3.3mW (typ. ).
  • IDT71V321L.
  • Active: 250mW (typ. ).
  • Standby: 660µW (typ. ).
  • Two INT flags for port-to-port communications.
  • On-chip port arbitration logic.
  • BUSY output flag.
  • Fully asynchronous operation from either port.
  • Battery backup operation.
  • 2V data retention.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT-71V-321L.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V321L
Manufacturer Integrated Device Technology
File Size 210.69 KB
Description HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM
Datasheet download datasheet IDT71V321L Datasheet

Full PDF Text Transcription

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HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT Integrated Device Technology, Inc. IDT71V321S/L FEATURES: • High-speed access —Commercial: 25/35/55ns (max.) • Low-power operation —IDT71V321S —Active: 250mW (typ.) —Standby: 3.3mW (typ.) —IDT71V321L —Active: 250mW (typ.) —Standby: 660µW (typ.) • Two INT flags for port-to-port communications • On-chip port arbitration logic • BUSY output flag • Fully asynchronous operation from either port • Battery backup operation—2V data retention • TTL-compatible, single 3.3V ± 0.3V power supply • Available in popular plastic packages DESCRIPTION: The IDT71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications.
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