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IDT71V3557SA - 3.3V Synchronous ZBT SRAMs

Download the IDT71V3557SA datasheet PDF. This datasheet also covers the IDT71V3557S variant, as both devices belong to the same 3.3v synchronous zbt srams family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronou

Features

  • 128K x 36, 256K x 18 memory configurations.
  • Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access).
  • ZBTTM Feature - No dead cycles between write and read cycles.
  • Internally synchronized output buffer enable eliminates the need to control OE.
  • Single R/W (READ/WRITE) control pin.
  • 4-word burst capability (Interleaved or linear).
  • Individual byte write (BW1 - BW4) control (May tie active).
  • Three chip enables for simple depth expansion.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71V3557S-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V3557SA
Manufacturer IDT
File Size 299.10 KB
Description 3.3V Synchronous ZBT SRAMs
Datasheet download datasheet IDT71V3557SA Datasheet

📁 Similar Datasheet

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Other Datasheets by IDT

Part Number Description
IDT71V3557S 3.3V Synchronous ZBT SRAMs
IDT71V3556XS 3.3V Synchronous ZBT SRAMs
IDT71V3556XSA 3.3V Synchronous ZBT SRAMs
IDT71V3558XS 3.3V Synchronous ZBT SRAMs
IDT71V3558XSA 3.3V Synchronous ZBT SRAMs

Full PDF Text Transcription

Click to expand full text
128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs IDT71V3557S IDT71V3559S IDT71V3557SA IDT71V3559SA Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRITE) control pin ◆ 4-word burst capability (Interleaved or linear) ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ Three chip enables for simple depth expansion ◆ 3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ) ◆ Optional Boundary Scan JTAG Interface (IEEE 1149.
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