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IDT71V2578SA - 128K X 36/ 256K X 18 3.3V Synchronous SRAMs 2.5V I/O/ Pipelined Outputs/ Burst Counter/ Single Cycle Deselect

Download the IDT71V2578SA datasheet PDF. This datasheet also covers the IDT-71V variant, as both devices belong to the same 128k x 36/ 256k x 18 3.3v synchronous srams 2.5v i/o/ pipelined outputs/ burst counter/ single cycle deselect family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT71V2576/78 are high-speed SRAMs organized as 128K x 36/256K x 18.

The IDT71V2576/78 SRAMs contain write, data, address and control registers.

Internal logic allows the SRAM to generate a selftimed write based upon a decision which can be left until the end of the write cycle.

Features

  • 128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial and Industrial:.
  • 150MHz 3.8ns clock access time.
  • 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O Optional - Boundary Scan JTAG Interface (IEEE 1149.1 compliant) Packaged in a JEDEC Standard 100-pin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT-71V-2576S.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V2578SA
Manufacturer Integrated Device Technology
File Size 282.49 KB
Description 128K X 36/ 256K X 18 3.3V Synchronous SRAMs 2.5V I/O/ Pipelined Outputs/ Burst Counter/ Single Cycle Deselect
Datasheet download datasheet IDT71V2578SA Datasheet

Full PDF Text Transcription

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128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect x x IDT71V2576S IDT71V2578S IDT71V2576SA IDT71V2578SA Features 128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial and Industrial: – 150MHz 3.8ns clock access time – 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O Optional - Boundary Scan JTAG Interface (IEEE 1149.
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