Datasheet4U Logo Datasheet4U.com

ICSLV810 - Buffer/Clock Driver

Description

The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout buffer.

This device is specifically designed for data communications clock management.

The large fanout from a single input line reduces loading on the input clock.

Features

  • Packaged in 20-pin QSOP/SSOP.
  • Split 1:10 fanout Buffer.
  • Maximum skew between outputs of different.
  • packages 0.75 ns Max propagation delay of 3.8 ns Operating voltage of 1.5 V to 2.5 V on Bank A Operating voltage of 1.5 V to 2.5 V on Banks B and C Advanced, low power, CMOS process Industrial temperature range -40° C to +85° C 3.3 V tolerant input when VDDA=2.5 V Available in Pb (lead) free packaging.

📥 Download Datasheet

Datasheet Details

Part number ICSLV810
Manufacturer Integrated Circuit Systems
File Size 274.21 KB
Description Buffer/Clock Driver
Datasheet download datasheet ICSLV810 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICSLV810 BUFFER - CLOCK DRIVER Integrated Device Technolog
ICS-40180 Low-Noise Microphone InvenSense
ICS-40300 High SPL Analog Microphone InvenSense
ICS-40310 Low-Noise Microphone InvenSense
ICS-40618 High Dynamic Range Microphone InvenSense

Other Datasheets by Integrated Circuit Systems

Part Number Description
ICSLV218 Dual 1-to-8 Low Voltage Clock Buffer/Translator
ICS1522 User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
ICS1523 High-Performance Programmable Line-Locked Clock Generator
ICS1524 Dual Output Phase Controlled SSTL-3/PECL Clock Generator
ICS1526 Video Clock Synthesizer

Full PDF Text Transcription

Click to expand full text
ICSLV810 www.DataSheet4U.com Buffer/Clock Driver Description The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout buffer. This device is specifically designed for data communications clock management. The large fanout from a single input line reduces loading on the input clock. The TTL level outputs reduce noise levels on the part. Typical applications are clock and signal distribution. Features • Packaged in 20-pin QSOP/SSOP • Split 1:10 fanout Buffer • Maximum skew between outputs of different • • • • • • • packages 0.75 ns Max propagation delay of 3.8 ns Operating voltage of 1.5 V to 2.5 V on Bank A Operating voltage of 1.5 V to 2.5 V on Banks B and C Advanced, low power, CMOS process Industrial temperature range -40° C to +85° C 3.3 V tolerant input when VDDA=2.
Published: |