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ICS952702 - Programmable Timing Control Hub for K7 System

Description

The ICS952702 is a two chip clock solution for desktop designs using SIS 746 style chipsets.

When used with a zero delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals for such a system.

Features

  • 1 - Pair of differential open drain CPU outputs.
  • 1 - Single-ended open drain CPU output.
  • 8 - PCICLK @ 3.3V including 2 PCI clock free running.
  • 2 - AGPCLK @ 3.3V.
  • 3 - REF @ 3.3V.
  • 2 - ZCLK @ 3.3V.
  • 2 - IOAPIC @ 2.5V.
  • 1 - 12_48MHz @ 3.3V.
  • 1 - 24_48MHz @ 3.3V Key Specifications:.
  • CPU Output Jitter.

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Datasheet Details

Part number ICS952702
Manufacturer Integrated Circuit Systems
File Size 149.47 KB
Description Programmable Timing Control Hub for K7 System
Datasheet download datasheet ICS952702 Datasheet

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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICS952702 Programmable Timing Control Hub for K7TM System Recommended Application: SiS746/746FX style chipset Output Features: • 1 - Pair of differential open drain CPU outputs • 1 - Single-ended open drain CPU output • 8 - PCICLK @ 3.3V including 2 PCI clock free running • 2 - AGPCLK @ 3.3V • 3 - REF @ 3.3V • 2 - ZCLK @ 3.3V • 2 - IOAPIC @ 2.5V • 1 - 12_48MHz @ 3.3V • 1 - 24_48MHz @ 3.3V Key Specifications: • CPU Output Jitter <250ps • AGP Output Jitter <250ps • ZCLK Output Jitter <250ps • PCI Output Jitter <500ps • CPU-AGP/PCI/ZCLK skew: 2.5ns~3.
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