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ICS9248-112 - Frequency Generator & Integrated Buffers

Description

The ICS9248-112 is the single chip clock solution for designs using the 810/810E style chipset.

It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming.

Features

  • 2- CPUs @2.5V, up to 150MHz.
  • 9 - SDRAM @ 3.3V, up to150MHz including 1 free running.
  • 8 - PCICLK @ 3.3V.
  • 1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz.
  • 2 - 3V66MHz @ 3.3V, 2X PCI MHz.
  • 1- 48MHz, @3.3V fixed.
  • 1- 24MHz, @3.3V fixed.
  • 1- REF @3.3V, 14.318MHz. Features:.
  • Up to 166MHz frequency support.
  • Support FS0-FS3 strapping status bit for I2C read back.
  • Support power management: Through Power down Mode fro.

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Datasheet Details

Part number ICS9248-112
Manufacturer Integrated Circuit Systems
File Size 384.61 KB
Description Frequency Generator & Integrated Buffers
Datasheet download datasheet ICS9248-112 Datasheet

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Other Datasheets by Integrated Circuit Systems

Part Number Description
ICS9248-110 Frequency Generator & Integrated Buffers
ICS9248-114 Frequency Generator & Integrated Buffers
ICS9248-101 Frequency Generator & Integrated Buffers
ICS9248-103 Frequency Generator & Integrated Buffers
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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICS9248-112 Preliminary Product Preview Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: 810/810E type chipset. Output Features: • 2- CPUs @2.5V, up to 150MHz. • 9 - SDRAM @ 3.3V, up to150MHz including 1 free running • 8 - PCICLK @ 3.3V • 1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz • 2 - 3V66MHz @ 3.3V, 2X PCI MHz • 1- 48MHz, @3.3V fixed. • 1- 24MHz, @3.3V fixed • 1- REF @3.3V, 14.318MHz. Features: • Up to 166MHz frequency support • Support FS0-FS3 strapping status bit for I2C read back. • Support power management: Through Power down Mode from I2C programming. • Spread spectrum for EMI control ( ± 0.25% center). • Spread can be enabled or disabled to all 32 frequencies throuth I2C. • Uses external 14.
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