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74AUC1G02 - 74AUC1G02 Single 2-input NOR gate

General Description

The 74AUC1G02is a high-performance, low-power, low-voltage, Si-gate CMOS device.

Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using Ioff.

Key Features

  • Wide supply voltage range from 0.8 to 2.7 V.
  • Performance optimised for VCC = 1.8 V.
  • High noise immunity.
  • Complies with JEDEC standard:.
  • JESD76 (1.65 to 1.95 V).
  • 8 mA output drive (VCC = 1.65 V).
  • CMOS low power consumption.
  • Latch-up performance exceeds 250 mA.
  • ESD protection: 2000 V Human Body Model (A 114-A) 200 V Machine Model (A 115-A).
  • 3.3 V tolerant inputs/outputs.
  • SC-88A and SC-74A package. Q.

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Datasheet Details

Part number 74AUC1G02
Manufacturer Integrated Circuit Solution Inc
File Size 50.08 KB
Description 74AUC1G02 Single 2-input NOR gate
Datasheet download datasheet 74AUC1G02 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET 74AUC1G02 Single 2-input NOR gate Preliminary specification File under Integrated Circuits, IC24 2002 Nov 12 Philips Semiconductors Preliminary specification Single 2-input NOR gate FEATURES • Wide supply voltage range from 0.8 to 2.7 V • Performance optimised for VCC = 1.8 V • High noise immunity • Complies with JEDEC standard: – JESD76 (1.65 to 1.95 V) • 8 mA output drive (VCC = 1.65 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • ESD protection: 2000 V Human Body Model (A 114-A) 200 V Machine Model (A 115-A) • 3.3 V tolerant inputs/outputs • SC-88A and SC-74A package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; input slewrate ≥ 1 V/ns. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs A and B to output Y CONDITIONS VCC = 0.