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HYB39S256400CTL - (HYB39S256xxxCT) 256 MBit Synchronous DRAM

Download the HYB39S256400CTL datasheet PDF. This datasheet also covers the HYB39S256800CT variant, as both devices belong to the same (hyb39s256xxxct) 256 mbit synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

HYB 39S256400CT-7.5 HYB 39S256400CT-8 HYB 39S256800CT-7.5 HYB 39S256800CT-8 HYB 39S256160CT-7.5 HYB 39S256160CT-8 HYB39S256xx0CTL PC133-333-520 PC100-222-620 PC133-333-520 PC100-222-620 PC133-333-520 PC100-222-620 PC100-xxx-620 P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP

Features

  • 01 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS,.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYB39S256800CT_InfineonTechnologies.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HYB39S256400CTL
Manufacturer Infineon
File Size 509.95 KB
Description (HYB39S256xxxCT) 256 MBit Synchronous DRAM
Datasheet download datasheet HYB39S256400CTL Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HYB39S256400 (HYB39S256xxx) 256 MBit Synchronous DRAM Siemens Semiconductor
HYB39S256400T (HYB39S256xxx) 256 MBit Synchronous DRAM Siemens Semiconductor
HYB39S256160 (HYB39S256xxx) 256 MBit Synchronous DRAM Siemens Semiconductor
HYB39S256160T (HYB39S256xxx) 256 MBit Synchronous DRAM Siemens Semiconductor
HYB39S256800 (HYB39S256xxx) 256 MBit Synchronous DRAM Siemens Semiconductor

Other Datasheets by Infineon

Part Number Description
HYB39S256400CT (HYB39S256xxxCT) 256 MBit Synchronous DRAM
HYB39S256400DC (HYB39S256xxxD) 256 MBit Synchronous DRAM
HYB39S256400DCL (HYB39S256xxxD) 256 MBit Synchronous DRAM
HYB39S256400DT (HYB39S256xxxD) 256 MBit Synchronous DRAM
HYB39S256400DTL (HYB39S256xxxD) 256 MBit Synchronous DRAM

Full PDF Text Transcription

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HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -7.5 fCK tCK3 tAC3 tCK2 tAC2 133 7.5 5.4 10 6 -8 125 8 6 10 6 Units MHz ns ns ns ns • • • • • • • • • • • • Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7,8 µs) Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface versions Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) -7.
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