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IS64LPS25636A - Single CYCLE DESELECT STATIC RAM

Download the IS64LPS25636A datasheet PDF. This datasheet also covers the IS61LPS51218A variant, as both devices belong to the same single cycle deselect static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

IS64LPS25636A and IS61LPS/VPS51218A are highspeed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth ex- pansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JTAG Boun.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61LPS51218A-ISSI.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS64LPS25636B 9Mb Single CYCLE DESELECT STATIC RAM
IS64LPS25618EC SINGLE CYCLE DESELECT SRAM
IS64LPS204818B 36Mb Single CYCLE DESELECT STATIC RAM
IS64LPS102436B 36Mb Single CYCLE DESELECT STATIC RAM
IS64LPS12832EC SINGLE CYCLE DESELECT SRAM
IS64LPS12836EC SINGLE CYCLE DESELECT SRAM
IS64LF12832A (IS6xxFxxxxxA) Synchronous Flow-through Static RAM
IS64LF12832EC SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836A (IS6xxFxxxxxA) Synchronous Flow-through Static RAM
IS64LF12836EC SYNCHRONOUS FLOW-THROUGH SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM JANUARY 2014 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth ex- pansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for BGA package • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.