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IS64LF12832A - (IS6xxFxxxxxA) Synchronous Flow-through Static RAM

Download the IS64LF12832A datasheet PDF. This datasheet also covers the IS61LF12832A variant, as both devices belong to the same (is6xxfxxxxxa) synchronous flow-through static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

Copyright © 2005 Integrated Silicon Solution, Inc.

All rights reserved.

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • Power Supply LF: VDD 3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61LF12832A_ISSI.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS64LF12832EC SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836A (IS6xxFxxxxxA) Synchronous Flow-through Static RAM
IS64LF12836EC SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF25618A (IS6xxFxxxxxA) Synchronous Flow-through Static RAM
IS64LF25618EC SYNCHRONOUS FLOW-THROUGH SRAM
IS64LPS102436B 36Mb Single CYCLE DESELECT STATIC RAM
IS64LPS12832EC SINGLE CYCLE DESELECT SRAM
IS64LPS12836EC SINGLE CYCLE DESELECT SRAM
IS64LPS204818B 36Mb Single CYCLE DESELECT STATIC RAM
IS64LPS25618EC SINGLE CYCLE DESELECT SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
( DataSheet : www.DataSheet4U.com ) IS61(64)LF12832A IS64VF12832A IS61(64)LF12836A IS61(64)VF12836A IS61(64)LF25618A IS61(64)VF25618A 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM ISSI PRELIMINARY INFORMATION AUGUST 2005 ® FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VF: VDD 2.5V -5% +10%, VDDQ 2.